問題詳情

5 若欲使用 Verilog 語言合成（synthesize）出與下圖相同功能的電路，則下列各 Verilog 模組何者正確？  
(A)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X;reg Y;always @(posedge clock) X <= A | B;always @(B or C) Y = B & C; endmodule
(B)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X;reg Y;always @(posedge clock) X <= A | B;always @(posedge clock) Y = B & C; endmodule
(C)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X;wire Y;always @(posedge clock) X = A | B;always @(posedge clock) Y = B & C;endmodule
(D)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X;reg Y;always @(posedge clock) X <= A+B;always @(B or C) Y = B * C;endmoduleD XYABCclock

參考答案

答案：A
難度：非常困難0.175573
統計：A(23),B(35),C(35),D(13),E(0)

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